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SPANSION MCP
Data Sheet
TM
September 2003
TM
This document specifies SPANSION memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a SPANSION revisions will occur when appropriate, and changes will be noted in a revision summary.
TM
product. Future routine
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about SPANSION solutions.
TM
memory
FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50307-1E
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
16M (x8/x16) FLASH MEMORY & 4M (x8/x16) STATIC RAM
MB84VD2118XEM-70/MB84VD2119XEM-70
s FEATURES
* Power Supply Voltage of 2.7 V to 3.3 V * High Performance 70 ns maximum access time (Flash) 70 ns maximum access time (SRAM) * Operating Temperature -40 C to +85 C * Package 56-ball FBGA
(Continued)
s PRODUCT LINE-UP
Part No. Supply Voltage(V) Max Address Access Time (ns) Max CE Access Time (ns) Max OE Access Time (ns) MB84VD2118XEM/MB84VD2119XEM VCCf*= 3.0 V 70 70 30
+0.3 V -0.3 V
VCCs*= 3.0 V +0.3V -0.3 V 70 70 35
*: Both VCCf and VCCs must be in recommended operation range when either part is being accessed.
s PACKAGE
56-ball plastic FBGA
(BGA-56P-M02)
MB84VD2118XEM/2119XEM-70
(Continued)
* FLASH MEMORY * Simultaneous Read/Write Operations (Dual Bank) Miltiple devices available with different bank sizes (Please refer to ORDERING INFORMATION) Host system can program or erase in one bank, then immediately and simultaneously read from the other bank Zero latency between read and write operations Read-while-erase Read-while-program * Minimum 100,000 Write/Erase Cycles * Sector Erase Architecture Eight 4 K words and thirty one 32 K words. Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VD2118XEM: Top sector MB84VD2119XEM: Bottom sector * Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit Feature for Detection of Program or Erase Cycle Completion * Ready-Busy Output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic Sleep Mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC Write Inhibit 2.5 V * HiddenROM Region 64K byte of HiddenROM, accessible through a new "HiddenROM Enable" command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) * WP/ACC Input Pin At VIL, allows protection of boot sectors, regardless of sector protection/unprotection status (MB84VD2118XEM:SA37,SA38 MB84VD2119XEM:SA0,SA1) At VIH, allows removal of boot sector protection At VACC, program time will reduse by 40%. * Erase Suspend/Resume Suspends the erase operation to allow a read in another sector within the same device * Please refer to "MBM29DL16XTE/BE" Datasheet in Detailed Function * SRAM * Power Dissipation Operating : 40 mA Max Standby : 10 A Max * Power Down Features using CE1s and CE2s * Data Retention Supply Voltage: 1.5 V to 3.3 V * CE1s and CE2s Chip Select * Byte Data Control: LB (DQ7 to DQ0), UB (DQ15 to DQ8) * : Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
2
MB84VD2118XEM/2119XEM-70
s PIN ASSIGNMENT
(Top View) Marking side
B8 A15 A7 A11 A6 A8 A5 WE A4 B7 A12 B6 A19 B5 CE2s B4
C8 N.C. C7 A13 C6 A9 C5 N.C. C4 RY/BY C3 A18 C2 A5 C1 A2
D8 N.C. D7 A14 D6 A10
E8 A16 E7 SA E6 DQ6
F8 CIOf F7 DQ15/A-1 F6 DQ13 F5
G8 Vss G7 DQ7 G6 DQ12 G5 Vccs G4 Vccf G3 DQ10 G2 DQ0 G1 CE1s H7 DQ14 H6 DQ5 H5 CIOs H4 DQ11 H3 DQ2 H2 DQ8
INDEX LAND*
DQ4 F4 DQ3
WP/ACC RESET A3 LB A2 A7 B3 UB B2 A6 B1 A3
D3 A17 D2 A4 D1 A1
E3 DQ1 E2 VSS E1 A0
F3 DQ9 F2 OE F1 CEf
* : There is no solder ball. This land should be open electrically. (BGA-56P-M02)
3
MB84VD2118XEM/2119XEM-70
s PIN DESCRIPTION
Pin Name A17 to A0 A19, A18, A-1 SA DQ15 to DQ0 CEf CE1s CE2s OE WE RY/BY UB LB CIOf Function Address Inputs (Common) Address Input (Flash) Address Input (SRAM) Data Inputs / Outputs (Common) Chip Enable (Flash) Chip Enable (SRAM) Chip Enable (SRAM) Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Flash) Open Drain Output Upper Byte Control (SRAM) Lower Byte Control (SRAM) I/O Configuration (Flash) CIOf=VCCf is Word mode ( x16), CIOf=VSS is Byte mode ( x 8) I/O Configuration (SRAM) CIOs=VCCs is Word mode ( x16), CIOs=VSS is Byte mode ( x 8) Hardware Reset Pin / Sector Protection Unlock (Flash) Write Protect / Acceleration (Flash) No Internal Connection Device Ground (Common) Device Power Supply (Flash) Device Power Supply (SRAM) I/O I I I I/O I I I I I O I I I
CIOs
I
RESET WP/ACC N.C. VSS VCCf VCCs
I I -- Power Power Power
4
MB84VD2118XEM/2119XEM-70
s BLOCK DIAGRAM
VCCf A19 to A0 A19 to A0 A-1 WP/ACC RESET CEf CIOf VSS RY/BY
16 M bit Flash Memory DQ15/A-1 to DQ0
DQ15/A-1 to DQ0 VCCs A17 to A0 DQ15 to DQ0 VSS
SA LB UB WE OE CE1s CE2s CIOs
4 M bit Static RAM
5
MB84VD2118XEM/2119XEM-70
s DEVICE BUS OPERATIONS
User Bus Operations Table (Flash=Word mode; CIOf=VCCf, SRAM=Word mode; CIOs=VCCs) Operation *1, *3 CEf CE1s CE2s OE H X L H X H X H X L X L H X L X L X L H WE SA LB UB WP/ DQ7 to DQ0 DQ15 to DQ8 RESET ACC *5 High-Z High-Z High-Z High-Z DOUT DIN DOUT High-Z DOUT DIN High-Z DIN X High-Z High-Z High-Z High-Z DOUT DIN DOUT DOUT High-Z DIN DIN High-Z X VID X H X H X H H X X H X H X
Full Standby
H H
X H X H L H
X H X H H L
X X X X X X
X X H X X X L
X X H X X X L L H L L H X
Output Disable L Read from Flash *2 Write to Flash L L
Read from SRAM
H
L
H
X
H L L
Write to SRAM Temporary Sector Group Unprotection *4 Flash Hardware Reset Boot Block Sector Write Protection
H
L
H
X
L
X
H L
X
X H X X
X X L X
X
X
X
X
X X
X X
X X
X X
X X
X X
High-Z X
High-Z X
L X
X L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9 V) ; Program time will reduce by 40%.
6
MB84VD2118XEM/2119XEM-70
User Bus Operations Table (Flash=Word mode; CIOf=VCCf, SRAM=Byte mode; CIOs=VSS) Operation *1, *3 CEf CE1s CE2s OE H X L H X H X H X L L X H X X X L H X L X L X L H H X X L X WE SA LB UB WP/ DQ7 to DQ0 DQ15 to DQ8 RESET ACC *5 High-Z High-Z High-Z High-Z DOUT DIN DOUT DIN X High-Z High-Z High-Z High-Z DOUT DIN High-Z High-Z X H H H H VID X X X X X H X H X
Full Standby
H H
X H X H L H L X X
X H X H H L H L X
X X X X X X SA SA X
X X H X X X X X X
X X H X X X X X X
Output Disable L Read from Flash *2 Write to Flash Read from SRAM Write to SRAM Temporary Sector Group Unprotection *4 Flash Hardware Reset Boot Block Sector Write Protection L L H H X
X X
X X
X X
X X
X X
X X
High-Z X
High-Z X
L X
X L
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9 V); Program time will reduce by 40%.
7
MB84VD2118XEM/2119XEM-70
User Bus Operations Table (Flash=Byte mode; CIOf=VSS, SRAM=Byte mode; CIOs=VSS) Operation *1,*3 CEf CE1s CE2s DQ15/A-1 OE WE SA H X L H X H X H X L L X H X X L H X L X L X L H H X X L LB UB DQ7 to DQ0 High-Z High-Z High-Z High-Z DOUT DIN DOUT DIN X WP/ DQ14 to RESET ACC DQ8 *5 High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z X H H H H VID X X X X X H X H X
Full Standby
H H
X X X A-1 A-1 A-1 X X X
X H X H L H L X X
X H X H H L H L X
X X X X X X SA SA X
X X H X X X X X X
X X H X X X X X X
Output Disable L Read from Flash *2 Write to Flash Read from SRAM Write to SRAM Temporary Sector Group Unprotection *4 Flash Hardware Reset L L H H X
X
X
X
X
X
X
X
High-Z
High-Z X
L X
X L
Boot Block Sector X X X X X X X X X X Write Protection Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels. *1 : Other operations except for indicated this column are inhibited. *2 : WE can be VIL if OE is VIL, OE at VIH initiates the write operations. *3 : Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time. *4 : It is also used for the extended sector group protections. *5 : WP/ACC = VIL; protection of boot sectors. WP/ACC = VIH; removal of boot sectors protection. WP/ACC = VACC (9 V); Program time will reduce by 40%.
8
MB84VD2118XEM/2119XEM-70
s ABSOLUTE MAXIMUM RATINGS
Parameter Storage Temperature Ambient Temperature with Power Applied Voltage with Respect to Ground All pins except RESET, WP/ACC *1 VCCf/VCCs Supply *1 RESET *
2 3
Symbol Tstg TA VIN, VOUT VCCf,VCCs VIN VIN
Rating Min -55 -40 -0.3 -0.3 -0.5 -0.5 Max +125 +85 VCCf +0.4 VCCs +0.4 +4.0 + 13.0 +10.5
Unit C C V V V V V
WP/ACC *
*1 : Minimum DC voltage on input or I/O pins is -0.3 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf+0.4 V or VCCs+0.4 V. During voltage transitions, input or I/O pins may overshoot to VCCf+2.0 V or VCCs+2.0 V for periods of up to 20 ns. *2 : Minimum DC input voltage on RESET pin is -0.5 V. During voltage transitions, RESET pins may undershoot VSS to -2.0 V for periods of up to 20 ns. Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed +9.0 V. Maximum DC input voltage on RESET pins is +13.0 V which may overshoot to +14.0 V for periods of up to 20 ns. *3 : Minimum DC input voltage on WP/ACC pin is -0.5 V. During voltage transitions, WP/ACC pin may undershoot Vss to -2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Ambient Temperature VCCf/VCCs Supply Voltages Symbol TA Vccf, Vccs Value Min -40 +2.7 Max +85 +3.3 Unit C V
Note : Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
9
MB84VD2118XEM/2119XEM-70
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics
Parameter Input Leakage Current Output Leakage Current RESET Inputs Leakage Current
Symbol
Test Conditions VIN = VSS to VCCf, VCCs VOUT = VSS to VCCf, VCCs VCCf = VCCf Max,VCCs = VCCs Max, RESET = 12.5 V tCYCLE = 5 MHz Byte tCYCLE = 5 MHz Word tCYCLE = 1 MHz Byte tCYCLE = 1 MHz Word
Value Min -1.0 -1.0 -- -- -- -- -- -- Byte Word Byte Word -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max +1.0 +1.0 35 13 15 7 7 35 48 50 48 50 35 20
Unit A A A mA mA mA mA mA mA mA
ILI ILO ILIT
Flash VCC Active Current (Read) *1
ICC1f
CEf = VIL, OE = VIH
Flash VCC Active Current (Program/Erase) *2 Flash VCC Active Current (Read-While-Program) *5 Flash VCC Active Current (Read-While-Erase) *5 Flash VCC Active Current (Erase-Suspend-Program) ACC Input Leakage Current SRAM VCC Active Current
ICC2f ICC3f ICC4f ICC5f ILIA
CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH CEf = VIL, OE = VIH VCCf = VCCf Max,VCCs = VCCs Max, WP/ACC = VACC Max VCCs = VCCs Max, CE1s = VIL, CE2s = VIH tCYCLE =10 MHz
ICC1s
-- -- -- --
-- -- -- 1
40 40 8 5
mA mA mA A A
SRAM VCC Active Current
ICC2s
tCYCLE = 10 MHz CE1s = 0.2 V, CE2s = VCCs - 0.2 V tCYCLE = 1 MHz VCCf = VCCf Max, CEf = VCCf 0.3 V, RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCCf Max, RESET = VSS 0.3 V, WP/ACC = VCCf 0.3 V VCCf = VCCf Max, CEf = VSS 0.3 V, RESET = VCCf 0.3 V, WP/ACC = VCCf 0.3 V, VIN = VCCf 0.3 V or VSS 0.3 V CE1s > VCCs - 0.2 V, CE2s > VCCs - 0.2 V, LB = UB > VCCs-0.2 V or < 0.2 V CE1s > VCCs - 0.2 V or < 0.2 V, CE2s < 0.2 V, LB = UB > VCCs - 0.2 V or < 0.2 V
Flash VCC Standby Current Flash VCC Standby Current (RESET) Flash VCC Current (Automatic Sleep Mode) *3 SRAM VCC Standby Current SRAM VCC Standby Current
ISB1f
ISB2f
--
1
5
ISB3f
--
1
5
A
ISB1s
--
--
10
A A
ISB2s
--
--
10
(Continued)
10
MB84VD2118XEM/2119XEM-70
(Continued)
Parameter Input Low Level Input High Level Voltage for Sector Protection, and Temporary Sector Unprotection (RESET) *4 Voltage for Program Acceleration (WP/ACC) *4 SRAM Output Low Level SRAM Output High Level Flash Output Low Level Flash Output High Level Flash Low VCCf Lock-Out Voltage Symbol VIL VIH Test Conditions -- -- Value Min -0.3 2.4 Typ -- -- Max 0.5 VCC+0.3 Unit V V
VID
--
11.5
--
12.5
V
VACC VOL VOH VOL VOH VLKO
-- VCCs = VCCs Min, IOL=4.0 mA VCCs = VCCs Min, IOH=-0.5 mA VCCf = VCCf Min, IOL=4.0 mA VCCf = VCCf Min, IOH=-0.5 mA --
8.5 -- 2.4 -- 2.4 2.3
9.0 -- -- -- -- --
9.5 0.45 -- 0.4 -- 2.5
V V V V V V
* 1 : The ICC current listed includes both the DC operating current and the frequency dependent component. *2 : ICC active while Embedded Algorithm (program or erase) is in progress. *3 : Automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : Applicable for only VCCf applying. *5 : Embedded Alogorithm (program or erase) is in progress. (@5 MHz)
11
MB84VD2118XEM/2119XEM-70
2. AC Characteristics
* CE Timing Symbol Parameter JEDEC CE Recover Time * Timing Diagram for alternating SRAM to Flash -- Standard tCCR Test Setup -- Value Unit Min 0 Max -- ns
CEf
tCCR
tCCR
CE1s
tCCR
tCCR
CE2s
* Flash Characteristics Please refer to "s16M FLASH MEMORY CHARACTERISTICS for MCP" part. * SRAM Characteristics, Please refer to "s4M SRAM CHARACTERISTICS for MCP" part.
12
MB84VD2118XEM/2119XEM-70
s 16M FLASH MEMORY CHARACTERISTICS for MCP
1. Flexible Sector-erase Architecture on Flash Memory
* Eight 4 K words, and thirty one 32 K words. * Individual-sector, multiple-sector, or bulk-erase capability.
Bank size 4 Bank size 3 Bank size 2 Bank size 1
Word mode SA38 : 8KB (4KW) SA37 : 8KB (4KW) SA36 : 8KB (4KW) SA35 : 8KB (4KW) SA34 : 8KB (4KW) SA33 : 8KB (4KW) SA32 : 8KB (4KW) SA31 : 8KB (4KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 64KB (32KW) SA6 : 64KB (32KW) SA5 : 64KB (32KW) SA4 : 64KB (32KW) SA3 : 64KB (32KW) SA2 : 64KB (32KW) SA1 : 64KB (32KW) SA0 : 64KB (32KW) 0FFFFFh 0FF000h 0FE000h 0FD000h 0FC000h 0FB000h 0FA000h 0F9000h 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 000000h
Byte mode 1FFFFFh 1FE000h 1FC000h 1FA000h 1F8000h 1F6000h 1F4000h 1F2000h 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 000000h
Bank 1 Bank 1 Bank 1 Bank 1
Bank 2 Bank 2 Bank 2 Bank 2
Sector Architecture (Top Boot Block)
(Continued)
13
MB84VD2118XEM/2119XEM-70
(Continued)
Bank size 4
Bank size 3
Bank size 2
Bank size 1
Bank 2 Bank 2 Bank 2
Bank 2
Bank 1 Bank 1
Bank 1 Bank 1
SA38 : 64KB (32KW) SA37 : 64KB (32KW) SA36 : 64KB (32KW) SA35 : 64KB (32KW) SA34 : 64KB (32KW) SA33 : 64KB (32KW) SA32 : 64KB (32KW) SA31 : 64KB (32KW) SA30 : 64KB (32KW) SA29 : 64KB (32KW) SA28 : 64KB (32KW) SA27 : 64KB (32KW) SA26 : 64KB (32KW) SA25 : 64KB (32KW) SA24 : 64KB (32KW) SA23 : 64KB (32KW) SA22 : 64KB (32KW) SA21 : 64KB (32KW) SA20 : 64KB (32KW) SA19 : 64KB (32KW) SA18 : 64KB (32KW) SA17 : 64KB (32KW) SA16 : 64KB (32KW) SA15 : 64KB (32KW) SA14 : 64KB (32KW) SA13 : 64KB (32KW) SA12 : 64KB (32KW) SA11 : 64KB (32KW) SA10 : 64KB (32KW) SA9 : 64KB (32KW) SA8 : 64KB (32KW) SA7 : 8KB (4KW) SA6 : 8KB (4KW) SA5 : 8KB (4KW) SA4 : 8KB (4KW) SA3 : 8KB (4KW) SA2 : 8KB (4KW) SA1 : 8KB (4KW) SA0 : 8KB (4KW)
Word mode 0FFFFFh 0F8000h 0F0000h 0E8000h 0E0000h 0D8000h 0D0000h 0C8000h 0C0000h 0B8000h 0B0000h 0A8000h 0A0000h 098000h 090000h 088000h 080000h 078000h 070000h 068000h 060000h 058000h 050000h 048000h 040000h 038000h 030000h 028000h 020000h 018000h 010000h 008000h 007000h 006000h 005000h 004000h 003000h 002000h 001000h 000000h
Byte mode 1FFFFFh 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h 0D0000h 0C0000h 0B0000h 0A0000h 090000h 080000h 070000h 060000h 050000h 040000h 030000h 020000h 010000h 00E000h 00C000h 00A000h 008000h 006000h 004000h 002000h 000000h
Sector Architecture (Bottom Boot Block)
14
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=1) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (Byte mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (Word mode)
000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh
0D0000h to 0DFFFFh 068000h to 06FFFFh
Bank 2
SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 1F0000h to 1F1FFFh 1F2000h to 1F3FFFh 0F0000h to 0F7FFFh 0F8000h to 0F8FFFh 0F9000h to 0F9FFFh
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
Bank 1
15
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=1) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 001FFFh 002000h to 003FFFh 004000h to 005FFFh 006000h to 007FFFh 008000h to 009FFFh 00A000h to 00BFFFh 00C000h to 00DFFFh 00E000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh
Bank 1
0D0000h to 0DFFFFh 068000h to 06FFFFh
Bank 2
SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
16
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=2) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh
0C0000h to 0CFFFFh 060000h to 067FFFh 0D0000h to 0DFFFFh 068000h to 06FFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh
Bank 2
180000h to 18FFFFh 0C0000h to 0C7FFFh 190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1F0000h to 1F1FFFh 1F2000h to 1F3FFFh 0F8000h to 0F8FFFh 0F9000h to 0F9FFFh
Bank 1
SA33 SA34 SA35 SA36 SA37 SA38
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
17
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=2) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 001FFFh 002000h to 003FFFh 004000h to 005FFFh 006000h to 007FFFh 008000h to 009FFFh 00A000h to 00BFFFh 00C000h to 00DFFFh 00E000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh
Bank 1
SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
0C0000h to 0CFFFFh 060000h to 067FFFh 0D0000h to 0DFFFFh 068000h to 06FFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh
Bank 2
180000h to 18FFFFh 0C0000h to 0C7FFFh 190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
18
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=3) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh
Bank 2
0C0000h to 0CFFFFh 060000h to 067FFFh 0D0000h to 0DFFFFh 068000h to 06FFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh
180000h to 18FFFFh 0C0000h to 0C7FFFh 190000h to 19FFFFh 0C8000h to 0CFFFFh 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh 1F0000h to 1F1FFFh 1F2000h to 1F3FFFh 0F8000h to 0F8FFFh 0F9000h to 0F9FFFh
Bank 1
SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
1F4000h to 1F5FFFh 0FA000h to 0FAFFFh 1F6000h to 1F7FFFh 0FB000h to 0FBFFFh 1F8000h to 1F9FFFh 0FC000h to 0FCFFFh 1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
19
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=3) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 001FFFh 002000h to 003FFFh 004000h to 005FFFh 006000h to 007FFFh 008000h to 009FFFh 00A000h to 00BFFFh 00C000h to 00DFFFh 00E000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFhh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh
Bank 1
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank 2
20
MB84VD2118XEM/2119XEM-70
Sector Address Table (Top Boot Block, Bank Size=4) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1
Address Range (WORD mode)
000000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0F8FFFh 0F9000h to 0F9FFFh 0FA000h to 0FAFFFh 0FB000h to 0FBFFFh 0FC000h to 0FCFFFh
A17
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
A16
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1
A14
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 0 0 1 1 1 1
A13
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 1 1
A12
X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 000000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1F1FFFh 1F2000h to 1F3FFFh 1F4000h to 1F5FFFh 1F6000h to 1F7FFFh 1F8000h to 1F9FFFh
Bank 2
Bank 1
SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
1FA000h to 1FBFFFh 0FD000h to 0FDFFFh 1FC000h to 1FDFFFh 0FE000h to 0FEFFFh 1FE000h to 1FFFFFh 0FF000h to 0FFFFFh
21
MB84VD2118XEM/2119XEM-70
Sector Address Table (Bottom Boot Block, Bank Size=4) Sector Address Bank Sector A19
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bank Address A18
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Address Range (BYTE mode) A15
0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Address Range (WORD mode)
000000h to 000FFFh 001000h to 001FFFh 002000h to 002FFFh 003000h to 003FFFh 004000h to 004FFFh 005000h to 005FFFh 006000h to 006FFFh 007000h to 007FFFh 008000h to 00FFFFh 010000h to 017FFFh 018000h to 01FFFFh 020000h to 027FFFh 028000h to 02FFFFh 030000h to 037FFFh 038000h to 03FFFFh 040000h to 047FFFh 048000h to 04FFFFh 050000h to 057FFFh 058000h to 05FFFFh 060000h to 067FFFh 068000h to 06FFFFh 070000h to 077FFFh 078000h to 07FFFFh 080000h to 087FFFh 088000h to 08FFFFh 090000h to 097FFFh 098000h to 09FFFFh 0A0000h to 0A7FFFh 0A8000h to 0AFFFFh 0B0000h to 0B7FFFh 0B8000h to 0BFFFFh 0C0000h to 0C7FFFh 0C8000h to 0CFFFFh 0D0000h to 0D7FFFh 0D8000h to 0DFFFFh 0E0000h to 0E7FFFh 0E8000h to 0EFFFFh 0F0000h to 0F7FFFh 0F8000h to 0FFFFFh
A17
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
A16
0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
A14
0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A13
0 0 1 1 0 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
A12
0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 000000h to 001FFFh 002000h to 003FFFh 004000h to 005FFFh 006000h to 007FFFh 008000h to 009FFFh 00A000h to 00BFFFh 00C000h to 00DFFFh 00E000h to 00FFFFh 010000h to 01FFFFh 020000h to 02FFFFh 030000h to 03FFFFh 040000h to 04FFFFh 050000h to 05FFFFh 060000h to 06FFFFh 070000h to 07FFFFh 080000h to 08FFFFh 090000h to 09FFFFh 0A0000h to 0AFFFFh 0B0000h to 0BFFFFh 0C0000h to 0CFFFFh 0D0000h to 0DFFFFh 0E0000h to 0EFFFFh 0F0000h to 0FFFFFh 100000h to 10FFFFh 110000h to 11FFFFh 120000h to 12FFFFh 130000h to 13FFFFh 140000h to 14FFFFh 150000h to 15FFFFh 160000h to 16FFFFh 170000h to 17FFFFh 180000h to 18FFFFh 190000h to 19FFFFh 1A0000h to 1AFFFFh 1B0000h to 1BFFFFh 1C0000h to 1CFFFFh 1D0000h to 1DFFFFh 1E0000h to 1EFFFFh 1F0000h to 1FFFFFh
Bank 1
SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Bank 2
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MB84VD2118XEM/2119XEM-70
Sector Group Addresses Table (Top Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 A18 0 0 0 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 A16 0 0 1 1 X X X X X X 0 0 1 1 1 1 1 1 1 1 1 A15 0 1 0 1 X X X X X X 0 1 0 1 1 1 1 1 1 1 1 A14 X X X X X X X X X X X X X 0 0 0 0 1 1 1 1 A13 X X X X X X X X X X X X X 0 0 1 1 0 0 1 1 A12 X X X X X X X X X X X X X 0 1 0 1 0 1 0 1 Sectors SA0 SA1 to SA3 SA4 to SA7 SA8 to SA11 SA12 to SA15 SA16 to SA19 SA20 to SA23 SA24 to SA27 SA28 to SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
Sector Group Addresses Table (Bottom Boot Block) Sector Group SGA0 SGA1 SGA2 SGA3 SGA4 SGA5 SGA6 SGA7 SGA8 SGA9 SGA10 SGA11 SGA12 SGA13 SGA14 SGA15 SGA16 A19 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 A18 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 1 A17 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 A16 0 0 0 0 0 0 0 0 0 1 1 X X X X X X 0 0 1 1 A15 0 0 0 0 0 0 0 0 1 0 1 X X X X X X 0 1 0 1 A14 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X A13 0 0 1 1 0 0 1 1 X X X X X X X X X X X X X A12 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X Sectors SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 to SA10 SA11 to SA14 SA15 to SA18 SA19 to SA22 SA23 to SA26 SA27 to SA30 SA31 to SA34 SA35 to SA37 SA38
23
MB84VD2118XEM/2119XEM-70
Flash Memory Autoselect Codes Table Type Manufacturer's Code Top Boot Block Bank Size=1 Bottom Boot Block Bank Size=1 Top Boot Block Bank Size=2 Bottom Boot Block Bank Size=2 Top Boot Block Bank Size=3 Bottom Boot Block Bank Size=3 Top Boot Block Bank Size=4 Bottom Boot Block Bank Size=4 Sector Group protect *1: A-1 is for Byte mode. *2: Output 01h at protected sector address and output 00h at unprotected sector address. Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word A12 to A19 X X X X X X X X X Sector Group Address A6 VIL VIL VIL VIL VIL VIL VIL VIL VIL A1 VIL VIL VIL VIL VIL VIL VIL VIL VIL A0 VIL VIH VIH VIH VIH VIH VIH VIH VIH A-1*1 VIL VIL X VIL X VIL X VIL X VIL X VIL X VIL X VIL X VIL Code (HEX) 04h 36h 2236h 39 2239h 2D 222Dh 2E 222Eh 28h 2228h 2Bh 222Bh 33h 2233h 35 2235h 01h*2
Device Code
VIL
VIH
VIL
24
MB84VD2118XEM/2119XEM-70
Flash Memory Command Definitions Table
Command Sequence Read/Reset *1 Read/Reset *1 Word Byte Word Autoselect Byte Program Word Byte Word Byte Word Byte 4 3 AAAh 555h AAAh 555h AAAh 555h AAAh BA BA 555h AAAh XXXh AAh Bus First Bus Second Bus Write Write Cycle Write Cycle Cycles Req'd Addr. Data Addr. Data 1 3 XXXh 555h AAAh 555h AAh 555h 2AAh 555h 2AAh 555h 2AAh 555h -- -- 2AAh 555h PA 55h F0h AAh -- 2AAh 555h 2AAh 55h -- 55h Third Bus Write Cycle Addr. -- 555h AAAh (BA) 555h (BA) AAAh 555h AAAh 555h AAAh 555h AAAh -- -- 555h AAAh -- Fourth Bus Read/Write Cycle Fifth Bus Write Cycle Sixth Bus Write Cycle
Data Addr. Data Addr. Data Addr. Data -- F0h -- RA -- RD -- -- -- -- -- -- -- --
90h
--
--
--
--
--
--
A0h
PA 555h AAAh 555h AAAh -- -- --
PD
-- 2AAh 555h 2AAh 555h -- -- --
--
-- 555h AAAh SA -- -- --
--
Chip Erase
6
AAh
55h
80h
AAh
55h
10h
Sector Erase Sector Erase Suspend Sector Erase Resume Set to Fast Mode Fast Program*2 Reset from Fast Mode *2 Extended Sector Group Protection *3 Query *4 HiddenROM Entry HiddenROM Program *5 HiddenROM Erase *5
6 1 1
AAh B0h 30h AAh
55h -- -- 55h
80h -- -- 20h
AAh -- -- --
55h -- -- --
30h -- -- --
Word Byte Word Byte Word Byte Word
3
2
A0h
PD F0h *6 60h
--
--
--
--
--
--
--
2
BA
90h
XXXh
--
--
--
--
--
--
--
--
4 Byte Word Byte Word Byte Word Byte Word Byte Word 4 Byte 1
XXXh 55h AAh 555h AAAh 555h AAAh 555h AAAh 555h
60h
SPA
SPA
40h
SPA
SD
--
--
--
--
98h
-- 2AAh 555h 2AAh 555h 2AAh 555h 2AAh
--
-- 555h AAAh 555h AAAh 555h AAAh (HRBA) 555h (HRBA) AAAh
--
--
--
--
--
--
--
3
AAh
55h
88h
--
--
--
--
--
--
4
AAh
55h
A0h
PA 555h AAAh
PD
-- 2AAh 555h
--
--
--
6
AAh
55h
80h
AAh
55h
HRA
30h
HiddenROM Exit *5
AAh AAAh 555h
55h
90h
XXXh
00h
--
--
--
--
25
MB84VD2118XEM/2119XEM-70
*1: Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. *2: This command is valid while Fast Mode. *3: This command is valid while RESET=VID. *4: The valid Address is A6 to A0. *5: This command is valid while HiddenROM mode. *6: The data "00h" is also acceptable. Notes : * Address bits A12 to A19 = X = "H" or "L" for all address commands except for Program Address (PA), Sector Address (SA),and Bank Address (BA). Bus operations are defined in "User Bus Operations". RA = Address of the memory location to be read. PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the write pulse. * SA = Address of the sector to be erased. The combination of A19, A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. BA = Bank address (A15 to A19) SPA = Sector group address to be protected. Set sector group address (SGA) and (A6, A1, A0) = (0, 1, 0). HRA = Address of the HiddenROM area. Top Boot Block Word mode : 0F8000h to 0FFFFFh Byte mode : 1F0000h to 1FFFFFh Bottom Boot Block Word mode : 000000h to 007FFFh Byte mode : 000000h to 00FFFFh HRBA = Bank address of the HiddenROM area. Top Boot Block : A15 = A16 = A17 = A18 = A19 = A20 = 1 Bottom Boot Block : A15 = A16 = A17 = A18 = A19 = A20 = 0 RD = Data read from location RA during read operation. PD = Data to be programmed at location PA. SD = Sector protection verify data. Output 01h at protected sector addresses and output 00h at unprotected sector addresses. * The system should generate the following address patterns; Word mode : 555h or 2AAh to addresses A10 to A0 Byte mode : AAAh or 555h to addresses A10 to A0 and A-1
26
MB84VD2118XEM/2119XEM-70
* Read Only Operations Characteristics (Flash) Symbol Parameter JEDEC Standard Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time From Addresses, CEf or OE, Whichever Occurs First RESET Pin Low to Read Mode * : Test Conditions Output Load : 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels : 0.0 V or 3.0 V Timing measurement reference level Input : 1.5 V Output : 1.5 V tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- tRC tACC tCEf tOE tDF tDF tOH tREADY
Test Setup -- CEf = VIL OE = VIL OE = VIL -- -- -- -- --
Value* Min 70 -- -- -- -- -- 0 -- Max -- 70 70 30 25 25 -- 20
Unit ns ns ns ns ns ns ns s
27
MB84VD2118XEM/2119XEM-70
* Read Cycle (Flash)
tRC
Address Stable
Address
tACC
CEf
tOE tDF
OE
tOEH
WE
tCEf
DQ
High-Z
Output Valid
High-Z
tRC
Address
tACC
Address Stable
CEf
tRH
tRP
tRH
tCEf
RESET
tOH
DQ
High-Z
Output Valid
28
MB84VD2118XEM/2119XEM-70
* Erase/Program Operations (Flash) Parameter Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time to CEf Low During Toggle Bit Polling Address Hold Time (WE to Addr.) Address Hold Time from CEf or OE High During Toggle Bit Polling Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Symbol JEDEC Standard tAVAV tAVWL -- tWLAX -- tDVWH tWHDX -- -- -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- -- -- tWC tAS tASO tAH tAHT tDS tDH tOES tOEH tCEPH tOEPH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVLHT tVIDR tVACCR tRB tRP tEOE tRH tBUSY tTOW tSPD Min 70 0 12 45 0 30 0 0 0 10 20 20 0 0 0 0 0 0 35 35 25 25 -- -- -- 50 4 500 500 0 500 -- 200 -- 50 -- Value Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 16 1 -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 70 -- 90 -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s s s ns ns ns ns ns ns ns s s 29
CEf High During Toggle Bit Polling OE High During Toggle Bit Polling Read Recover Time Before Write (OE to CEf) Read Recover Time Before Write (OE to WE) WE Setup Time (CEf to WE) CEf Setup Time (WE to CEf) WE Hold Time (CEf to WE) CEf Hold Time (WE to CEf) Write Pulse Width CEf Pulse Width Write Pulse Width High CEf Pulse Width High Byte Programming Operation Word Programming Operation Sector Erase Operation * VCCf Setup Time Voltage Transition Time *2 Rise Time to VID *2 Rise Time to VACC Recover Time from RY/BY RESET Pulse Width Delay Time from Embedded Output Enable RESET Hold Time Before Read Program/Erase Valid to RY/BY Delay Erase Time-out Time *3 Erase Suspend Transition Time *4
1
MB84VD2118XEM/2119XEM-70
*1 : This does not include the preprogramming time. *2 : This timing is for Sector Protection Operation. *3 : The time between writes must be less than "tTOW" otherwise that command will not be accepted and erasure will start. A time-out or "tTOW" from the rising edge of last CEf or WE whichever happens first will initiate the execution of the Sector Erase command(s). *4 : When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum of "tSPD" to suspend the erase operation.
30
MB84VD2118XEM/2119XEM-70
* Write Cycle (WE control) (Flash)
3rd Bus Cycle
Data Polling
PA tAS tAH PA tRC
Address
555h tWC
CEf
tCS tCH tCEf
OE
tGHWL tWP tWPH tWHWH1 tOE
WE
tDS tDH tOH
DQ
A0h
PD
DQ7
DOUT
DOUT
Notes : * * * * * *
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
31
MB84VD2118XEM/2119XEM-70
* Write Cycle (CEf control) (Flash)
3rd Bus Cycle
Data Polling PA tAS tAH PA
Address
555h tWC
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CEf
tDS tDH
DQ
A0h
PD
DQ7
DOUT
Notes : * * * * * *
PA is address of the memory location to be programmed. PD is data to be programmed at byte address. DQ7 is the output of the complement of the data written to the device. DOUT is the output of the data written to the device. Figure indicates last two bus cycles out of four bus cycle sequence. These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
32
MB84VD2118XEM/2119XEM-70
* AC Waveforms Chip/Sector Erase Operations (Flash)
Address
555h tWC
2AAh tAS tAH
555h
555h
2AAh
SA*
CEf
tCS tCH
OE
tGHWL tWP tWPH
WE
tDS tDH AAh 55h 80h AAh 55h 30h for Sector Erase 10h/ 30h
DQ
tVCS
VCCf
* : SA is the sector address for Sector Erase. Addresses = 555h for Chip Erase. Note : These waveform are for the x16 mode. (The addresses differ from x8 mode.)
33
MB84VD2118XEM/2119XEM-70
* AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
CEf
tCH
tOE
tDF
OE
tOEH
WE
tCEf
* DQ7
Data In DQ7 DQ7 = Valid Data
High-Z
tWHWH1 or 2
High-Z
DQ (DQ6 to DQ0)
Data In tBUSY
DQ6 to DQ0 = Output Flag
DQ6 to DQ0 Valid Data
tEOE
RY/BY
* : DQ7 = Valid Data (The device has completed the Embedded operation.)
34
MB84VD2118XEM/2119XEM-70
* AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
Address
tAHT tASO tAHT tAS
CEf
tCEPH
WE
tOEH tOEPH tOEH
OE
tDH tOE Toggle Data Toggle Data tCEf * Toggle Data Stop Toggling Output Valid
DQ6/DQ2
Data
tBUSY
RY/BY
* : DQ6 stops toggling (The device has completed the Embedded operation).
35
MB84VD2118XEM/2119XEM-70
* Bank-to-bank Read/Write Timing Diagram (Flash)
Read
tRC
Command
tWC
Read
tRC
Command
tWC
Read
tRC
Read
tRC
Address Address
BA1
tAS
BA2 (555h)
tAH
BA1
tACC tCE
BA2 (PA)
BA1
tAS tAHT
BA2 (PA)
CEf CEf
tOE tCEPH
OE OE
tGHWL tWP tOEH tDF
WE WE
tDS tDH tDF
DQ DQ
Valid Output
Valid Intput (A0h)
Valid Output
Valid Intput (PD)
Valid Output
Status
Note : This is example of Read for Bank 1 and Embedded Algorithm (program) for Bank 2. BA1: Address of Bank 1. BA2: Address of Bank 2.
36
MB84VD2118XEM/2119XEM-70
* RY/BY Timing Diagram during Write/Erase Operations (Flash)
CEf
Rising edge of the last write pulse
WE
Entire programming or erase operations
RY/BY
tBUSY
* RESET, RY/BY Timing Diagram (Flash)
WE
RESET
tRP tRB
RY/BY
tREADY
37
MB84VD2118XEM/2119XEM-70
* Temporary Sector Unprotection (Flash)
VCCf tVCS VID VIH RESET
tVIDR tVLHT
CEf
WE tVLHT RY/BY Unprotection period Program or Erase Command Sequence tVLHT
* Acceleration Mode Timing Diagram (Flash)
VCCf tVCS VACC VIH WP/ACC
tVACCR tVLHT
CEf
WE tVLHT
tVLHT RY/BY Acceleration Mode Period
38
MB84VD2118XEM/2119XEM-70
* Extended Sector Protection (Flash)
VCCf tVCS
RESET tVIDR
tVLHT tWC tWC SGAx SGAx SGAy
Add
A0
A1
A6
CEf
OE TIME-OUT tWP
WE
Data
60h
60h
40h tOE
01h
60h
SGAx : Sector Group Address to be protected SGAy : Next Group Sector Address to be protected TIME-OUT : Time-Out window = 250 s (Min)
39
MB84VD2118XEM/2119XEM-70
2. Erase and Programming Performance (Flash)
Limit Parameter Min Sector Erase Time Byte Programming Time Word Programming Time Chip Programming Time Erase/Program Cycle -- -- -- -- 100,000 Typ 1 8 16 -- -- Max 10 300 360 50 -- s s s s cycle Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Excludes system-level overhead Unit Comment
40
MB84VD2118XEM/2119XEM-70
s 4M SRAM CHARACTERISTICS for MCP
1. AC Characteristics
* Read Cycle (SRAM) Parameter Read Cycle Time Address Access Time Chip Enable (CE1s) Access Time Chip Enable (CE2s) Access Time Output Enable Access Time LB, UB to Output Valid Chip Enable (CE1s Low and CE2s High) to Output Active Output Enable Low to Output Active UB, LB Enable Low to Output Active Chip Enable (CE1s High or CE2s Low) to Output High-Z Output Enable High to Output High-Z UB, LB Output Enable to Output High-Z Output Data Hold Time Note: Test Conditions Output Load:1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to VCCs Timing measurement reference level Input: 0.5xVCCs Output: 0.5xVCCs Symbol tRC tAA tCO1 tCO2 tOE tBA tCOE tOEE tBE tOD tODO tBD tOH Value Min 70 -- -- -- -- -- 5 0 0 -- -- -- 10 Max -- 70 70 70 35 70 -- -- -- 25 25 25 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
41
MB84VD2118XEM/2119XEM-70
* Read Cycle (SRAM)
tRC Address tAA tCO1 CE1s tCOE tCO2 CE2s tOD tOE OE tOEE tODO tOD tOH
LB, UB tBA tBE tCOE DQ Valid Data Out tBD
Note : WE remains "H" for the read cycle.
42
MB84VD2118XEM/2119XEM-70
* Write Cycle (SRAM) Parameter Write Cycle Time Write Pulse Width Chip Enable to End of Write Address valid to End of Write UB, LB to End of Write Address Setup Time Write Recovery Time WE Low to Output High-Z WE High to Output Active Data Setup Time Data Hold Time Symbol tWC tWP tCW tAW tBW tAS tWR tODW tOEW tDS tDH Value Min 70 50 55 55 55 0 0 -- 0 30 0 Max -- -- -- -- -- -- -- 25 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns
43
MB84VD2118XEM/2119XEM-70
* Write Cycle *3 (WE control) (SRAM)
tWC Address tAS tWP tWR
WE tAW tCW CE1s
CE2s
tCW
tBW LB, UB tODW tOEW
DOUT
*1
*2
tDS DIN
*4
tDH
*4
Valid Data In
*1 : If CE1s goes "L" (or CE2s goes "H") coincident with or after WE goes "L", the output will remain at High-Z. *2 : If CE1s goes "H" (or CE2s goes "L") coincident with or before WE goes "H", the output will remain at High-Z. *3 : If OE is "H" during the write cycle, the outputs will remain at High-Z. *4 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
44
MB84VD2118XEM/2119XEM-70
* Write Cycle *1 (CE1s control) (SRAM)
tWC Address tAS tWP tWR
WE tAW tCW CE1s
CE2s
tCW
tBW LB, UB tBE tCOE DOUT tDS tDH tODW
DIN
*2
Valid Data In
*1 : If OE is "H" during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
45
MB84VD2118XEM/2119XEM-70
* Write Cycle *1 (CE2s Control) (SRAM)
tWC Address tAS tWP tWR
WE
tCW CE1s
tAW CE2s tCW
tBW LB, UB tBE tCOE DOUT tDS DIN *2 tDH tODW
Valid Data In
*1 : If OE is "H" during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
46
MB84VD2118XEM/2119XEM-70
* Write Cycle *1 (LB, UB Control) (SRAM)
tWC Address tWP WE tWR
tCW CE1s
tCW CE2s tAW tAS tBW
LB, UB
tBE tCOE DOUT tDS *2 tDH Valid Data In tODW
DIN
*1 : If OE is "H" during the write cycle, the outputs will remain at High-Z. *2 : Because I/O signals may be in the output state at this Time, input signals of reverse polarity must not be applied.
47
MB84VD2118XEM/2119XEM-70
2. Data Retention Characteristics (SRAM)
Parameter Data Retention Supply Voltage Standby Current Chip Deselect to Data Retention Mode Time Recovery Time Note : tRC: Read cycle time * CE1s Controlled Data Retention Mode *1
VCCs DATA RETENTION MODE
Symbol VDH VDH = 1.5 V IDDS2 tCDR tR
Value Min 1.5 -- 0 tRC Typ -- 3 -- -- Max 3.3 10 -- --
Unit V A ns ns
2.7 V
*2 VIH VDH CE1s VCCS -0.2 V tCDR
*2
tR
GND
*1 : In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs-0.2 V or Vss to 0.2 V during data retention mode. Other input and input/output pins can be used between -0.3 V to Vccs+0.3 V. *2 : When CE1s is operating at the VIH Min level (2.2 V), the standby current is given by ISB1s during the transition of VCCs from 3.3 V to 2.2 V. * CE2s Controlled Data Retention Mode *
VCCs DATA RETENTION MODE
2.7 V
VDH VIH
CE2s
tCDR
tR
VIL
0.2 V
GND
* : In CE2s controlled data retention mode, input and input/output pins can be used between -0.3 V to Vccs+0.3 V. 48
MB84VD2118XEM/2119XEM-70
s PIN CAPACITANCE
Value Parameter Input Capacitance Output Capacitance Control Pin Capacitance WP/ACC Pin Capacitance Symbol CIN COUT CIN2 CIN3 Test Setup Typ VIN = 0 VOUT = 0 VIN = 0 VIN = 0 11 12 14 17 Max 14 16 16 20 pF pF pF pF Unit
Note : Test conditions TA = +25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please handle this package carefully since the sides of package create acute angles.
s CAUTION
* The high voltage (VID) cannot apply to address pins and control pins except RESET. Exception is when autoselect and sector group protect function are used, then the high voltage (VID) can be applied to RESET. * Without the high voltage (VID) , sector group protection can be achieved by using "Extended Sector Group Protection" command.
49
MB84VD2118XEM/2119XEM-70
s ORDERING INFORMATION
MB84VD2118 X EM -70 PBS
PACKAGE TYPE PBS = 56-ball FBGA SPEED OPTION See Product Selector Guide Device Revision (Valid Combination) EM
Bank Size 1 = 0.5 Mbit / 15.5 Mbit 2 = 2 Mbit / 14 Mbit 3 = 4 Mbit / 12 Mbit 4 = 8 Mbit / 8 Mbit
DEVICE NUMBER/DESCRIPTION 16 Mega-bit (2M x 8-bit or 1M x 16-bit) Dual Operation Flash Memory 3.0 V-only Read, Program, and Erase 4 Mega-bit (512K x 8-bit or 256K x 16-bit) SRAM BOOT CODE SECTOR ARCHITECTURE 84VD2118 = Top sector 84VD2119 = Bottom sector
50
MB84VD2118XEM/2119XEM-70
s PACKAGE DIMENSION
56-ball plastic FBGA (BGA-56P-M02)
7.200.10(.283.004) 0.20(.008) S B 1.09 -0.10 .043 -.004
+0.11 +.004
(Mounting height)
B 0.40(.016) REF 0.80(.031) REF 8 7 6 5 4 3 2 1 HGFEDCBA INDEX 56-o0.45 +0.10 -0.05 56-o.018 +.004 -.002 0.08(.003)
M
0.390.10 (Stand off) (.015.004) 0.80(.031) REF A 7.000.10 (.276.004)
0.40(.016) REF
S INDEX-MARK AREA 0.20(.008) S A
SAB
0.10(.004) S
C
2002 FUJITSU LIMITED B56002S-c-1-1
Dimensions in mm (inches) Note : The values in parentheses are regerence values.
51
MB84VD2118XEM/2119XEM-70
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party's intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0307 (c) FUJITSU LIMITED Printed in Japan

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